1. Field of the Invention
The present disclosure relates generally to a memory and, more particularly, a memory with one or more shared write bit lines.
2. Description of the Related Art
Today, most microprocessor systems employ a hierarchical memory structure. In a typical microprocessor system, a first-level (L1) cache memory (or cache), e.g., a high-speed static random access memory (SRAM), is incorporated within an integrated circuit (IC) that includes at least one central processing unit (CPU) core. A microprocessor system may also include one or more other levels (e.g., a second-level (L2) and a third-level (L3)) of cache coupled between the L1 cache and main memory, e.g., dynamic random access memory (DRAM). The L2 cache, the L3 cache and the main memory typically reside off-chip and are usually progressively slower and cheaper than the L1 cache. However, in some designs, multiple levels of cache are incorporated on-chip with one or more CPU cores. In any case, the caches hold a sub-set of information that corresponds to information stored in the main memory. When information (e.g., an instruction and/or data) addressed by the CPU is stored in the L1 cache (i.e., an L1 cache hit occurs), the information is retrieved directly from the L1 cache and, as such, the CPU can usually process the information without stalling. However, when information addressed by the CPU is not in the L1 cache (i.e., an L1 cache miss occurs), other levels of cache or the main memory are accessed to retrieve the information, which may take a relatively long time period. In this case, the CPU may stall until the information is returned from the other levels of cache or the main memory.
In order for a microprocessor system to function properly, it has been desirable to maintain memory coherency, i.e., coherency between cache(s) and main memory. For example, data stored in main memory should correspond to data that is cached. Memory coherency may be maintained by implementing a write-through or a write-back approach. In the write-through approach, when the CPU writes data to the cache, the same data is immediately written to the main memory. In general, the write-through approach is relatively simple to implement. However, the write-through approach is relatively slow as all data written to the cache is also immediately written to main memory, which may impact CPU performance. On the other hand, the write-back approach writes data in the cache to the main memory at a later time and, as such, it is desirable to implement a mechanism to track when the cache has been modified to maintain memory coherency.
Generally, caches are organized as a plurality of cache lines (also referred to as blocks). A size of a cache line is architecture dependent and may, for example, include 8, 16, 32, 64, 128, 256, or 512 bytes. One situation in which a cache line must be written to main memory to maintain memory coherency is when the cache line has been modified and the modified (dirty) cache line is being evicted from a cache to make room for a new cache line. Using the write-back approach, the dirty cache line is read from the cache and stored in the main memory, before the dirty cache line is replaced by a new cache line. Implementations of the write-back approach generally reduce bus traffic to main memory and generally deliver better performance and consume less power than the write-through approach. Reducing power consumption is particular beneficial in battery-operated devices, such as cellular telephones.
In a cache that employs the write-back approach, a status bit has been maintained to indicate whether a cache line has been modified. One status bit that has been employed to track whether a cache line has been modified has been referred to as a dirty bit. Another status bit that has been employed to indicate whether a cache line is valid has been referred to as a valid bit. The valid bit for each cache line is typically deasserted when the memory system is initialized, e.g., at power-on or at reset. Typically, a single dirty bit and a single valid bit have been employed for each cache line. In the usual case, the dirty bit has been asserted when any byte within an associated cache line has been modified. An asserted dirty bit has indicated that an associated cache line should be written-back to the main memory, when the cache line was evicted from the cache, for example, to make room for a new cache line.
A typical cache system includes three functional blocks: a cache controller, a tag memory, and an information memory (i.e., either a unified data and instruction memory or non-unified data and instruction memories with associated separate tag memories). To service a read request, the cache controller has read the tag memory to determine whether a requested address and its associated target information resided in the cache. When a cache hit occurred, the cache controller has caused the requested information to be provided from the cache. However, if the requested information was not present in the cache, the cache controller forwarded the request to the next level of memory hierarchy (e.g., main memory) in order to load the cache line with the requested information. To make room in the cache for the new information (instruction or data), the cache controller has selected (using, for example, a least recently used (LRU) replacement policy) a cache line in the cache for eviction. If the cache line being evicted from a write-back cache has been modified (as indicated by an asserted dirty bit), the cache controller has caused the modified cache line (or sub-line) to be written to the main memory. When the cache line of a write-back cache has not been modified, the cache controller has simply overwritten the cache line with the new information. To service a write request, the cache controller has determined (by comparing tags to an address) if addressed data was stored in the cache. If a cache hit occurred, the cache controller has updated the data in the cache. When servicing a write request for a write-back cache that experienced a cache hit, a dirty bit for an addressed cache line has been asserted to indicate that data in the addressed cache line has been modified.
Certain caches, in order to enhance efficiency of the caches, have combined tag bits and status bits within a single memory array. In at least some caches so designed, the status bits have been written to the cache in two phases of a cycle (i.e., using a dual phase write). That is, the status bit or bits have been written along with the tag bits of a cache line in a first phase and the status bit or bits have been written independently of the tag bits in a second phase (i.e., a status bit update phase). Unfortunately, implementing dual phase writes of the status bits of a cache has required the implementation of an additional pair of write bit lines and associated write bit line drivers, which has increased a size and power consumption of an associated integrated circuit. While two-way set associative memories have shared write bit lines between cells, cells of two-way set associate memories have not been updated using dual phase writes.
What is needed is a technique that reduces a size of write bit line column of a memory. It would also be desirable for the technique to reduce a power consumption of an associated integrated circuit.
In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced.